1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM), especially relates to a NAND-type flash memory.
2. Description of the Related Art
A NAND-type flash memory is known as one of EEPROMs. In the NAND-type flash memory, multiple memory cells are connected in series in such a way that adjacent two memory cells share a source/drain diffusion area, thereby constituting a NAND cell unit. Therefore, the unit cell area is made smaller than that of a NOR-type flash memory, and it is easy to achieve a large capacity. Further, since data write is performed with F-N tunneling current, the power consumption is small. As a result, it is possible to make the number of cells written at a time large, so that it is able to do substantially a high-speed write.
In the NAND-type flash memory, it is used such a self boost scheme that the “1” write NAND cell channel is effectively boosted for preventing “1” write cells (write-inhibiting cells) and other non-selected cells from being injected with electrons (for example, refer to Unexamined Japanese patent Application Publication No. 10-283788).
In the self boost scheme shown in the above-described publication, write voltage Vpgm is applied to a selected memory cell; 0[volts] to a source side neighbor non-selected memory cell; and write medium voltage Vm (<Vpgm) to the other non-selected memory cells. With this voltage application, at “1” data writing time, the selected cell's channel and the bit line side non-selected cells' channel are separated from the source line side cells' channel, and these channels are efficiently boosted.
However, in case the non-selected cell is set at 0[volts], which is disposed just adjacent to the selected cell with the write voltage Vpgm applied, a leakage current is generated due to band-to-band tunneling at the drain edge of the non-selected cell with the channel separating or isolating voltage, 0V, applied, and it is possible to cause erroneous write. In consideration of this point, it has already been provided such an improved self boost scheme that a few non-selected cells, to which a voltage slightly higher than 0V is applied, are disposed between the selected cell with the write voltage Vpgm applied and the non-selected cell with the channel-isolating voltage applied.
For example, explaining in detail, the second non-selected cell from the selected cell is set at 0[volts]; and the first non-selected cell neighboring the selected cell at Va (>0) [volts]. As a result, the channel region from the selected cell with Vpgm applied to the non-selected cell with 0V applied has such a potential distribution that is gradually decreased, resulting in that the selected cell's channel potential boosted by Vpgm is not directly applied to the drain edge of the non-selected cell with 0V applied, so that the erroneous write due to the band-to-band tunneling is suppressed.
However, in the self boost scheme provided in the prior art, there is remained a danger of write disturbance (erroneous write) in the non-selected cells.